Multi-level logic minimization using implicit don't cares

This paper describes a new approach for the minimization of multilevel logic circuits. We define a multilevel representation of a block of combinational logic called a Boolean network. We propose a procedure, ESPRESSO-MLD, to transform a given Boolean network into a prime, irredundant, and “R-minimal” form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. We introduce the new concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. We give theorems which prove the correctness of the proposed procedure. Finally, we show that prime and irredundant multilevel logic circuits are 100-percent testable for input and output single stuck faults, and that these tests are provided as a by-product of the mini-